Valavan Manohararajah

Rajah: The Design of a Chess Program. ICCA Journal, Vol. 20, No. 2, pp. 87-91.

With T. Borer, S. D. Brown, and Z. G. Vranesic. Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices. In Proceedings of the Conference on Field-Programmable Logic and Applications, Montpelier, France, September 2002, pp. 232-241.

With D. P. Singh and S. D. Brown. Post-Placement Functional Decomposition for FPGAs. In Proceedings of the International Workshop on Logic and Synthesis, Temecula, California, USA, June 2004, pp. 114-118.

With S. D. Brown and Z. G. Vranesic. Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping. In Proceedings of the International Workshop on Logic and Synthesis, Temecula, California, USA, June 2004, pp. 14-21.

With D. P. Singh and S. D. Brown. Incremental Retiming for FPGA Physical Synthesis. In Proceedings of the Design Automation Conference, Anaheim, California, USA, June 2005, pp. 433-438.

With A. Ling, D. P. Singh, and S. D. Brown. FPGA Architecture Evaluation and Technology Mapping using Boolean Satisfiability. In Proceedings of the International Workshop on Logic and Synthesis, Lake Arrowhead, California, USA, June 2005, pp. 399-406.

With D. P. Singh, and S. D. Brown. Timing Driven Functional Decomposition for FPGAs. In Proceedings of the International Workshop on Logic and Synthesis, Lake Arrowhead, California, USA, June 2005, pp. 415-422.

With D. P. Singh, and S. D. Brown. Two-Stage Physical Synthesis for FPGAs. Invited paper. In Proceedings of the IEEE Custom Integrated Circuits Conference, San Jose, California, USA, September 2005, pp. 171-178.

With D. P. Singh, and S. D. Brown. Post-Placement BDD-Based Decomposition for FPGAs. In Proceedings of the Conference on Field-Programmable Logic and Applications, Tampere, Finland, August 2005, pp. 31-38.

With G. R. Chiu, D. P. Singh, and S. D. Brown. Difficulty of Predicting Interconnect Delay in a Timing Driven FPGA CAD Flow. In Proceedings of the Workshop on System Level Interconnect Prediction, Munich, Germany, March 2006, pp. 3-8.

Physical Synthesis Challenges for FPGAs. Invited talk. Electronic Design Processes (EDPS), Monterey, California, USA, April 2006.

With S. D. Brown and Z. G. Vranesic. Adaptive FPGAs: High-Level Architecture and a Synthesis Method. In Proceedings of the Conference on Field Programmable Logic and Applications, Madrid, Spain, August 2006, pp. xx-xx.

Valavan Manohararajah

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